1. Field of the Invention
The present invention relates to a semiconductor device provided with a booster circuit.
2. Background Art
FIG. 15 is a circuit diagram of a booster circuit 10 housed in a conventional semiconductor device (JP2002-51538A, hereinafter, referred to as Patent literature 1).
The booster circuit 10 is provided with transistors QNA1 to QNAm connected in series between an input IN and an output OUT and capacitors CA1 to CAm whose one ends are respectively connected to the respective transistors QNA1 to QNAm. The other ends of the capacitors CA1 to CAm are connected to a clock supplying source via a voltage converting portion 12,
The voltage converting portion 12 has voltage converting circuits VB1 to VBm connected to respective other ends of the respective capacitors CA1 to CAm. The voltage converting circuits VB1 to VBm receive clock signals Φ and Φbar having phases opposed to each other alternately and they boosts voltages of these clock signals to supply them to the capacitors CA1 to CAm. Timing charts of the clock signal Φ and Φbar are illustrated in FIG. 17. Thereby, the booster portion 11 boosts the input voltage Vin to output an output voltage Vout higher than the input voltage Vin.
FIG. 16 is a circuit diagram illustrating a constitution of one (hereinafter, called “voltage converting circuit VB) of the voltage converting circuits VB1 to VBm. The voltage converting circuit VB has a plurality of boosting stages including capacitors CB1 to CBk whose one ends are connected to a voltage source Vin via n-type transistors QNB1 to QNBk and whose other ends are grounded via n-type transistors QNC1 to QNCk. The voltage converting circuit VB further has p-type transistors QPA1 to QPAk. The transistors QPA1 to QPAk can connect all the capacitors CB1 to CBk in series between input and output.
Since the transistors QNB1 to QNBk and QNC1 to QNCk, and the transistors QPA1 to QPAk are different in conductive type, they are alternately switched by the clock signal Φ or Φbar. When the clock signal Φ or Φbar is High, the respective capacitors CB1 to CBk are connected in parallel between the input voltage Vin and the ground, and when the clock signal Φ or Φbar is Low, the capacitors CB1 to CBk are connected in series between the input voltage Vin and the output CLKOUT. As illustrated in FIG. 17, according to repetition of the clock signal Φ or Φbar between High and Low, the voltage converting circuit VB boosts the input voltage Vin to output the same from the output CLKOUT to either of the other ends of the capacitor CA1 to CAm.
Now, it is preferable that a power source voltage supplied externally of the semiconductor device (hereinafter, also simply called “power source voltage”) is low for reducing power consumption. Conventionally, the power source voltage is lowered stepwise such as 5V and 3.3V (or 2.5V). In recent years, the power source voltage is further lowered from 3.3V to 1.8V. In such a transient term where the power source voltage is being lowered in this manner, a semiconductor device is required to accommodate a plurality of power source voltages with voltages different from one another.
Further, even in a semiconductor device corresponding to a single power source voltage in an ordinary operation, there occurs a case that a power source voltage higher than a power source voltage in the ordinary operation is used in a test step before shipping. For example, in order to make a judgement about an initial defective, a high voltage is used as a power source for accelerating failure in a burn-in step where a device is made defective by accelerating the defective condition. Thereby, it is preferable that the semiconductor device corresponds to a plurality of power source voltages with different voltages.
In general, in case that an operation of a semiconductor device is ensured when a power source voltage applied externally is in a range of Vccmin to Vccmax, such a design is made that the booster circuit outputs a desired output voltage when the power source voltage is Vccmin. An internal supply voltage (hereinafter, simply called “supply voltage”) Vin is an external power source voltage itself or a voltage obtained by voltage-reducing this voltage, and it increases/decreases depending on the power source voltage. Thereby, assuming that the supply voltage Vin is in a range of Vinmin to Vinmax, the booster circuit is designed such that the supply voltage Vin outputs a desired output voltage, when the supply voltage Vin is Vinmin. For example, when voltages with two different ranges of 1.8V and 3V are used as the power source voltage Vcc, such a setting can be made that Vin=1.5V in case of Vcc=1.8V range (Vcc=1.5V to 2V) and Vin=2.5V in case of Vcc=3V range (Vcc=2.5V to 3.6V). In this case, the booster circuit 10 is generally designed so as to output a desired output voltage in case of Vcc=1.5V, namely, Vin=1.5V.
In this case, however, when the power source voltage Vcc is on the side of the Vccmax, or when the power source voltage Vcc in the burn-in step is higher than Vccmax, if the supply voltage Vin is set to be High according to the power source voltage Vcc, the booster circuit 10 results in possession of an excessive boosting capacity. For example, in case that the booster circuit 10 is designed so as to output a desired output voltage in case of Vcc=1.5V and Vin=1.5V, the booster circuit 10 has an excessive capacity with setting of Vcc=3V and Vin=2.5V (>1.5V).
Further, when the supply voltage Vin is set to be higher according to a relatively high power source voltage Vcc, all the boosting stages in the voltage converting circuit VB are boosted on the basis of the supply voltage Vin, so that excessive voltages are applied to transistors in the voltage converting circuit VB. Therefore, some or all of the transistors QNB1 to QNBk must comprise high breakdown voltage transistors. Since the high breakdown voltage transistor has a lower conductance than that of a low breakdown voltage transistor, it is necessary to increase the size (the channel width) of the former transistor in order to maintain a conductance approximately equal to that of the low breakdown voltage transistor. As a result, since a parasitic capacitance increases, there occur a problem that an operation efficiency of the voltage converting circuit VB lowers and a problem that a circuit area of the booster circuit 10 becomes large.
In order to solves the above problem, for example, Vin can be set to 1.5V even in case of Vcc=3V. However, a voltage drop of Vcc=3V down to 1.5V causes waste of power, which is undesirable. That is, considering the power consumption in the range of Vcc=3V, a consumed current of a product corresponding to both Vcc=1.8V range and Vcc=3V range becomes larger than that of a product corresponding to only Vcc=3V range.